1. Field of the Invention
The present invention relates to a scan test technique of a semiconductor integrated circuit.
2. Description of the Related Art
In a scan test of a semiconductor integrated circuit, it is desirable that the test should be carried out in the same timing as a normal operating speed. In order to achieve the execution, it is necessary to carry out the test by using, as a clock, a delay pulse formed by two pulse waves having an interval which is almost equivalent to an operating clock. Such a test will be hereinafter referred to as a delay pulse test.
Conventionally, JP-A-8-201481 Publication has disclosed a technique for carrying out the delay pulse test at a high frequency which is equivalent to an internal clock. In the technique, a clock signal having a comparatively low frequency is input from an outside and a clock signal having a comparatively high frequency which is the same as that in the normal operation of a semiconductor integrated circuit is generated from an internal clock generating portion (for example, a PLL circuit) based on the input clock, thereby generating a delay pulse having a delay width which is equal to a cycle of an internal clock signal. If the scan test is carried out by using the generated delay pulse through the method, it is possible to perform an AC-based test which is the same as the normal operation of the semiconductor integrated circuit so that a problem of a clock skew can also be verified sufficiently.
With the conventional structure, however, a clock signal having a comparatively high frequency which is the same as that in the normal operation is generated in the internal clock generating portion. Therefore, a time is required for stabilizing the clock signal. Consequently, there is a possibility that an LSI inspection cost might be increased. In the case in which the PLL circuit is used, for example, there is a possibility that an effective failure diagnosis result cannot be obtained when a malfunction is caused by the PLL circuit. For this reason, it is necessary to add a test item for the PLL circuit.